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74HC27; 74HCT27
Triple 3-input NOR gate
Rev. 03 -- 7 January 2008 Product data sheet
1. General description
The 74HC27; 74HCT27 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC27; 74HCT27 provides the 3-input NOR function.
2. Features
s Multiple package options s Complies with JEDEC standard no. 7A s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V s Specified from -40 C to +85 C and from -40 C to +125 C
3. Ordering information
Table 1. Ordering information Temperature range Name 74HC27N 74HC27D 74HC27DB 74HC27PW 74HC27BQ -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C DIP14 SO14 SSOP14 TSSOP14 Description plastic dual in-line package; 14 leads (300 mil) plastic small outline package; 14 leads; body width 3.9 mm Version SOT27-1 SOT108-1 Type number Package
plastic shrink small outline package; 14 leads; body width SOT337-1 5.3 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1 quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm DIP14 SO14 plastic dual in-line package; 14 leads (300 mil) plastic small outline package; 14 leads; body width 3.9 mm SOT27-1 SOT108-1
74HCT27N 74HCT27D
-40 C to +125 C -40 C to +125 C
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
Table 1.
Ordering information ...continued Temperature range Name Description Version
Type number Package 74HCT27DB 74HCT27PW 74HCT27BQ -40 C to +125 C -40 C to +125 C -40 C to +125 C SSOP14 TSSOP14 plastic shrink small outline package; 14 leads; body width SOT337-1 5.3 mm plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1 quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm
4. Functional diagram
1 2 1 2 13 3 4 5 9 10 11 1A 1B 1C 2A 2B 2C 3A 3B 3C
mna936
1
12
1Y
12
13 3 4 1
6
2Y
6
5 9 A 1 8 B C Y
3Y
8
10 11
mna935
mna937
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram (one gate)
74HC_HCT27_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
2 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
5. Pinning information
5.1 Pinning
74HC27 74HCT27
terminal 1 index area 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 8 3A 3Y 1B 2A 2B 2C 2Y 2 3 4 5 6 7 GND 3Y 8 14 VCC 13 1C 12 1Y 11 3C 10 3B 9 3A
74HC27 74HCT27
1A 1B 2A 2B 2C 2Y GND
1 2 3 4 5 6 7
1
1A
001aag760
001aag759
Transparent top view
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input
Fig 4. Pin configuration DIP14, SO14, (T)SSOP14
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2. Symbol 1A 1B 2A 2B 2C 2Y GND 3Y 3A 3B 3C 1Y 1C VCC Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Description data input data input data input data input data input data output ground (0 V) data output data input data input data input data output data input supply voltage
74HC_HCT27_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
3 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
6. Functional description
Table 3. Inputs nA L X X H
[1] H = HIGH voltage level; L = LOW voltage level; X = don't care.
Function table[1] Outputs nB L X H X nC L H X X nY H L L L
7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation DIP14 package SO14, (T)SSOP14 and DHVQFN14 packages
[1] [2]
[2]
Conditions VI < -0.5 V or VI > VCC + 0.5 V VO < -0.5 V or VO > VCC + 0.5 V -0.5 V < VO < VCC + 0.5 V
[1] [1]
Min -0.5 -50 -65 -
Max +7 20 20 25 50 +150 750 500
Unit V mA mA mA mA mA C mW mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C. For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5. Symbol Type 74HC27 VCC VI VO supply voltage input voltage output voltage 2.0 0 0 5.0 6.0 VCC VCC V V V Recommended operating conditions Parameter Conditions Min Typ Max Unit
74HC_HCT27_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
4 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
Table 5. Symbol tr, tf
Recommended operating conditions ...continued Parameter input rise and fall times Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min -40 4.5 0 0 VCC = 4.5 V -40 Typ 6.0 5.0 6.0 Max 1000 500 400 +125 5.5 VCC VCC 500 +125 Unit ns ns ns C V V V ns C
Tamb Type 74HCT27 VCC VI VO tr, tf Tamb
ambient temperature supply voltage input voltage output voltage input rise and fall times ambient temperature
9. Static characteristics
Table 6. Static characteristics type 74HC27; 74HCT27 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74HC27 VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level VI = VIH or VIL output voltage IO = -20 A; VCC = 2.0 V IO = -20 A; VCC = 4.5 V IO = -20 A; VCC = 6.0 V IO = -4.0 mA; VCC = 4.5 V IO = -5.2 mA; VCC = 6.0 V VOL LOW-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC CI input leakage current VI = VCC or GND; VCC = 6.0 V 1.5 3.15 4.2 1.9 4.4 5.9 1.2 2.4 3.2 0.8 2.1 2.8 2.0 4.5 6.0 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 2.0 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1.0 20 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1.0 40 V V V V V V V V V V V V V V V V A A pF Conditions Min 25 C Typ Max -40 C to +85 C -40 C to +125 C Unit Min Max Min Max
3.98 4.32 5.48 5.81 0 0 0 0.15 0.16 3.5
supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V input capacitance
74HC_HCT27_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
5 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
Table 6. Static characteristics type 74HC27; 74HCT27 ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74HCT27 VIH VIL VOH HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V 2.0 1.6 1.2 0.8 2.0 0.8 2.0 0.8 V V Conditions Min 25 C Typ Max -40 C to +85 C -40 C to +125 C Unit Min Max Min Max
HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = -20 A IO = -4.0 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A IO = 4.0 mA input leakage current VI = VCC or GND; VCC = 5.5 V
4.4
4.5
0.1 0.26 0.1 2.0
4.4 3.84 -
0.1 0.33 1.0 20
4.4 3.7 -
0.1 0.4 1.0 40
V V V V A A
3.98 4.32 0 0.16 -
VOL
II ICC ICC
supply current VI = VCC or GND; VCC = 5.5 V; IO = 0 A additional per input pin; supply current VI = VCC - 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A nA, nB or nC inputs
-
150 3.5
540 -
-
675 -
-
735 -
A pF
CI
input capacitance
10. Dynamic characteristics
Table 7. Dynamic characteristics type 74HC27; 74HCT27 GND = 0 V; for load circuit see Figure 7. Symbol Parameter Conditions Min 74HC27 tpd propagation delay nA, nB, nC to nY; see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V tt transition time see Figure 6 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
[2] [1]
25 C Typ Max
-40 C to +125 C Unit Max (85 C) Max (125 C)
-
28 10 8 8 19 7 6
90 18 15 75 15 13
115 23 20 95 19 16
135 27 23 110 22 19
ns ns ns ns ns ns ns
74HC_HCT27_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
6 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
Table 7. Dynamic characteristics type 74HC27; 74HCT27 GND = 0 V; for load circuit see Figure 7. Symbol Parameter Conditions Min CPD 74HCT27 tpd propagation delay nA, nB, nC to nY; see Figure 6 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tt CPD transition time power dissipation capacitance VCC = 4.5 V; see Figure 6 per package; VI = GND to VCC - 1.5 V
[2] [3] [1]
25 C Typ 24 Max -
-40 C to +125 C Unit Max (85 C) Max (125 C) pF
power dissipation capacitance
per package; VI = GND to VCC
[3]
-
-
12 10 7 30
21 15 -
26 19 -
32 22 -
ns ns ns pF
[1] [2] [3]
tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs.
11. Waveforms
VI nA, nB, nC input GND tPHL VOH nY output VOL tTHL VY VM VX tTLH
001aag761
VM tPLH
Measurement points are given in Table 8. VOL and VOH are typical voltage output drop that occur with the output load.
Fig 6. Input (nA, nB, nC) to output (nY) propagation delays and output transition times Table 8. Type 74HC27 74HCT27 Measurement points Input VM 0.5VCC 1.3 V Output VM 0.5VCC 1.3 V VX 0.1VCC 0.1VCC VY 0.9VCC 0.9VCC
74HC_HCT27_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
7 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
VI negative pulse 0V
tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM
VI positive pulse 0V
VCC
VCC
PULSE GENERATOR
VI
VO
RL
S1
DUT
RT CL
open
001aad983
Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch
Fig 7. Load circuit for measuring switching times Table 9. Type 74HC27 74HCT27 Test data Input VI VCC 3V tr, tf 6 ns 6 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 k 1 k S1 position tPHL, tPLH open open
74HC_HCT27_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
8 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
12. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 14 8 MH wM (e 1)
pin 1 index E
1
7
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 8. Package outline SOT27-1 (DIP14)
74HC_HCT27_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
9 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A X
c y HE vMA
Z 14 8
Q A2 pin 1 index Lp 1 e bp 7 wM L detail X A1 (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3
0.010 0.057 inches 0.069 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.041 0.228 0.016
0.028 0.004 0.012
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 9. Package outline SOT108-1 (SO14)
74HC_HCT27_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
10 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
D
E
A X
c y HE vM A
Z 14 8
Q A2 A1 pin 1 index Lp L 1 bp 7 wM detail X (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 10. Package outline SOT337-1 (SSOP14)
74HC_HCT27_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
11 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o
Fig 11. Package outline SOT402-1 (TSSOP14)
74HC_HCT27_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
12 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm
D
B
A
A A1 E c
terminal 1 index area
detail X
terminal 1 index area e 2 L
e1 b 6 vMCAB wM C y1 C
C y
1 Eh 14
7 e 8
13 Dh 0
9 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
Fig 12. Package outline SOT762-1 (DHVQFN14)
74HC_HCT27_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
13 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
13. Abbreviations
Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic
14. Revision history
Table 11. Revision history Release date 20080107 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT27_CNV_2 Document ID 74HC_HCT27_3 Modifications:
* * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74HC27BQ and 74HCT27BQ (DHVQFN14 package) Product specification -
74HC_HCT27_CNV_2
19970828
74HC_HCT27_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
14 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
74HC_HCT27_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 7 January 2008
15 of 16
NXP Semiconductors
74HC27; 74HCT27
Triple 3-input NOR gate
17. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 7 January 2008 Document identifier: 74HC_HCT27_3

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